Clock Design Technology for High-Performance Processors

This paper introduces technology used in designing high-performance processors installed in servers so that they can distribute high-frequency clock signals among the whole chip. Clock synchronization systems must be designed so that clock signals can reach all synchronous sequential circuits in the processor at the same time. The influence of interconnect inductance cannot be ignored because clock frequencies have been getting higher, chip sizes have been getting larger, and lowresistance interconnects have appeared. Therefore, it is necessary to give sufficient consideration to inductance when designing such systems. The technology introduced in this paper uses both circuit design techniques to suppress clock skew and crosstalk noise, and CAD techniques which employ these techniques in an actual chip. The influence of inductance in clock transmission can be analyzed electrically by simulating actually designed clock circuits at the design stage, and this can help lead to higher performance processors.